1. Field of the Invention
The present invention relates to a magnetic memory device and, more particularly, to a data read circuit.
2. Description of the Related Art
A magnetic random access memory (MRAM) has a basic structure in which memory cells are arranged at the intersections between bit lines and word lines arranged in a matrix. Each memory cell includes a magnetic tunnel junction (MTJ) element, and a transistor which performs a switching operation. The MTJ element and the transistor are connected in series.
One terminal of each of the memory cells of the same row is connected to a bit line. The other terminal of each of the memory cells of the same column, i.e., the gate terminal of each transistor is connected to a word line. In data read, only transistors connected to a selected word line are turned on to form a current path. As a result, a current flows to only selected MTJ elements. This makes it possible to read data stored in the MTJ elements.
The operation of reading stored data is done by applying a predetermined driving voltage across each memory cell, and in this state, causing a sense amplifier to detect the current flowing to the bit line. For example, an MTJ element exhibits a low resistance when binary 0 is stored and a high resistance when binary 1 is stored. For this reason, a current flowing to a memory cell that stores binary 0 is larger than that flowing to a memory cell that stores binary 1. The sense amplifier compares a reference current with the current flowing to the memory cell, thereby determining whether the stored data is 0 or 1.
In the general read circuit of a conventional MRAM, sense amplifiers are individually connected to the bit lines, and data is read from each word line. However, the circuit scale of a sense amplifier is large, and it is therefore actually difficult to connect one sense amplifier to each bit line as the microfabrication and integration of the MRAM progress. A technique of coping with the high integration has been proposed, in which a plurality of adjacent bit lines share a sense amplifier, and connection of the sense amplifier and the bit lines is changed over using a switch to read data from each memory cell (e.g., Yoshihiro. UEDA et al., “Design of Low Read Bias Voltage and High Speed Sense Amplifier for STT-MRAM”, Technical Report of IEICE [referred to as Document 1, hereinafter]).
In the conventional MRAM read circuit described in Document 1, the circuit scale becomes smaller than that in the method of reading data for each word line by individually connecting sense amplifiers to the bit lines. However, since data is sequentially read from each memory cell, and switching between the bit lines and the sense amplifiers takes time, the read speed decreases.